AVS 46th International Symposium
    Plasma Science and Technology Division Monday Sessions
       Session PS-MoM

Invited Paper PS-MoM5
Sources of Plasma Induced Damage in Back-End VLSI Processing

Monday, October 25, 1999, 9:40 am, Room 609

Session: Plasma Damage
Presenter: S.W. Downey, Lucent Technologies, Bell Laboratories
Authors: S.W. Downey, Lucent Technologies, Bell Laboratories
D.W. Hwang, Lucent Technologies, Bell Laboratories
N. Layadi, Lucent Technologies, Bell Laboratories
P.W. Mason, Lucent Technologies, Bell Laboratories
A. Yen, Lucent Technologies, Bell Laboratories
V.M. Donnelly, Lucent Technologies, Bell Laboratories
M.V. Malyshev, Lucent Technologies, Bell Laboratories
J.I. Colonell, Praelux, Inc.
Correspondent: Click to Email
The possibility of plasma induced damage of devices during wafer processing exists in both etch and deposition steps using gaseous discharges. A variety of mechanisms exist for deleterious current flow through a thin (25 @Ao@) transistor gate oxide. Plasma induced damage, as measured by gate leakage currents or shifts in threshold voltages, are given for several etch and deposition processes. Device damage during metal etch is shown to be related to aspect ratio and measured electron temperature. Evidence of current or voltage-limited conditions can be extracted by modeling. Cleaning and photoresist stripping plasmas can also cause damage if not properly designed or operated. Charging of photoresist while stripping is shown to be avoidable. Damage from plasma based metal deposition tools and via etchers is also problematic and difficult to decouple. Data will show that damage is sensitive to both hardware and process parameters, but improved hardware can yield a larger damage free process window.