AVS 46th International Symposium
    Plasma Science and Technology Division Friday Sessions
       Session PS-FrM

Invited Paper PS-FrM1
Plasma Doping for Shallow Junctions

Friday, October 29, 1999, 8:20 am, Room 609

Session: Emerging Plasma Applications
Presenter: S.B. Felch, Varian Semiconductor Equipment Associates
Authors: S.B. Felch, Varian Semiconductor Equipment Associates
M.J. Goeckner, Varian Semiconductor Equipment Associates
Z. Fang, Varian Semiconductor Equipment Associates
G.C.-F. Yeap, AMD Inc.
D. Bang, AMD Inc.
M.-R. Lin, AMD Inc.
Correspondent: Click to Email
This paper reviews the characteristics of ultra-shallow junctions produced by Plasma Doping (PLAD). PLAD is one of the alternate doping techniques being developed for sub-0.18 µm devices. In the PLAD process, the substrate is placed directly in a plasma that contains the desired dopant ions. A negative-bias pulse is used to drive the dopant ions from the plasma into the substrate. Here, we describe results from a wide range of experiments aimed at the production of ultra-shallow junctions for sub-0.18 µm devices. For the results shown here, a BF@sub 3@ plasma was used to provide the dopant ions that were driven into 200-mm Si substrates using wafer biases ranging from -0.14 to -5.0 kV. The ultra-shallow junctions formed with this technique hav e been examined with both SIMS and electrical profiling techniques. Good sheet resistance uniformity, charging performance, and added contamination levels have been obtained. When PLAD is used in the production of sub-0.2 µm gate length pMOSFETs, one finds sub-threshold swing, off-state leakage, and hot-carrier reliability similar to beamline-implanted ones. In addition, higher drive currents are seen in the plasma-doped devices. These results together with the expected small footprint and low cost-of-ownership of such a system make PLAD an attractive doping technique.