AVS 45th International Symposium
    Thin Films Division Wednesday Sessions
       Session TF-WeM

Paper TF-WeM8
Sputtered Copper Seedlayer Processing Issues

Wednesday, November 4, 1998, 10:40 am, Room 310

Session: ULSI Metalization and Interconnects
Presenter: E.C. Cooney III, IBM Microelectronics
Authors: E.C. Cooney III, IBM Microelectronics
D.C. Strippe, IBM Microelectronics
J.W. Korejwa, IBM Microelectronics
A.H. Simon, IBM Microelectronics
C. Uzoh, IBM Microelectronics
Correspondent: Click to Email
One method to produce reliable Copper interconnects for advanced logic chip technology utilizes sputtered Copper seedlayers which are subsequently electroplated. However, experimental results indicate that good film step coverage as well as conformality are necessary to promote complete filling of the feature. Current trench dimensions and dual damascene aspect ratios are such that traditional sputter processes cannot adequately cover these structures. In addition, Copper tends to dewet from the substrate when thermal aspects of the process, such as sputter energy and deposition temperature, become too great. This can lead to a discontinuous film causing void formation during electrodeposition. We have investigated collimation of Copper films to improve the conformality in aggressive single and dual damascene structures. Collimation filters of various aspect ratio were used to deposit Copper seedlayers which were then filled using electrodeposition. In addition, thermal effects were examined through experimentation with lower DC magnetron powers coupled with special platen cooling considerations to reduce the heat load within the film. Electrical opens-yield and resistance data was then measured. Failure analysis was also performed to observe the plating fill.