AVS 45th International Symposium
    Thin Films Division Wednesday Sessions
       Session TF-WeM

Paper TF-WeM4
Investigation of the Structural and Chemical Stability of Advanced Metal Gate and Ultra-Thin Gate Dielectric Interfaces

Wednesday, November 4, 1998, 9:20 am, Room 310

Session: ULSI Metalization and Interconnects
Presenter: B. Claflin, North Carolina State University
Authors: B. Claflin, North Carolina State University
G. Lucovsky, North Carolina State University
Correspondent: Click to Email
Aggressive scaling of MOS device features to 0.1 µm and below will require the introduction of novel materials and new, low-thermal-budget processes. For example, in front end-of-the-line processing, alternative gate dielectrics such as ultra-thin SiO@sub 2@/Si@sub 3@N@sub 4@ stacks and/or high dielectric constant (K) materials such as Ta@sub 2@O@sub 5@ will be required to scale down the oxide equivalent thickness, t@sub ox@, and limit leakage current to acceptable levels. Likewise, replacements for heavily doped polycrystalline Si (poly-Si) gate electrodes such as simple or compound metals will be needed to prevent i) poly-depletion and ii) boron out-diffusion and dielectric penetration effects. However, the compatibility of these new materials under device processing conditions must be demonstrated. For example, many transition metals chemically react@footnote 1,2@ with SiO@sub 2@ at temperatures above 650@degree@C, and as such can not be used in gate stacks. In addition, the effects of thin film microstructure or phase transitions can dramatically alter the electronic and mechanical properties of these materials, and their interfaces, degrading both device performance and reliability. Recent studies@footnote 3,4@ indicate that TiN@sub x@ and WN@sub x@ composite metal gates are compatible with ultra-thin remote plasma-enhanced chemical-vapor deposited (RPECVD) SiO@sub 2@ and stacked SiO@sub 2@/Si@sub 3@N@sub 4@ gate dielectrics that are subjected to rapid thermal annealing (RTA); i.e., they perform well as metal gate electrode in MOS device structures. In this work, the structural integrity of these metal/dielectric interfaces subjected to RTA is investigated by SEM, TEM, and X-ray diffraction. These structural characterizations are correlated with the chemical stability of these interfaces determined by Auger electron spectroscopy (AES). Supported by NSF, SRC, and ONR. @FootnoteText@ @footnote 1@ S. Q. Wang and J. W. Mayer, J. Appl. Phys. 64, 4711 (1988). @footnote 2@ R. Pretorius, J. M. Harris, M-A. Nicolet, Solid State Electron. 21, 667 (1978). @footnote 3@ B. Claflin, M. Binger, and G. Lucovsky, J. Vac. Sci. Technol. A 16 (1998), in press. @footnote 4@ B. Claflin, M. Binger, and G. Lucovsky, Mat. Res. Soc. Symp. Proc. (1998), in press.