Among the most challenging tasks of plasma process technology today are, without doubt, plasma etching for fabrication of through-wafer interconnects in wafer stacks for vertical integration of chips (VIC) and plasma patterning of new materials used for electrodes and storage media in storage capacitors of Gbit scale DRAMs and FeRAMs. VIC realized by stacking and vertically interconnecting fully processed device wafers allows fabrication of both new systems with unique system qualities and systems with highly improved performance. 3D integration approaches are also driven by the interconnect crisis. Through wafer interconnects used for 3D chip integration require plasma etching of dielectrics, single cristal silicon, and interchip glue layers at aspect ratios exceeding 15 for vias through wafers thinned down to 15µm. Vertical profiles achieved with minimized RIE lags and high etch rates are the stringent requirements for all of these processes. Patterning of Pt electrodes is another challenging task. So far no volatile reaction products were obtained at usual process temperatures. Processes based on so-called reactive gases leading to a build-up of transient or removable sidewall films result in significant sidewall taper of the profiles and hence high CD gain whereas steep profile sidewalls have been obtained with processes based on inert gases with the tradeoff of build up of non-removable sidewall films. A new approach overcomes these tradeoffs by a combination of plasma patterning and CMP allowing fabrication of vertical Pt profiles with resist mask. The build-up of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the pre-etch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by CMP.