As LSI circuits continue to shrink, delay time of wiring caused by parasitic capacitance of interconnects becomes more important and further reduction becomes more difficult. Low-dielectric-constant (low-k) interlayer dielectrics (IL D) and low resistively wiring metals are now promising for reducing the RC delay of interconnects. Polymers are promisin g low-k materials. However, poor adhesion with Si substrates, poor thermal stability, and production difficulties have h indered their use in microelectronics. On the other hand, plasma-enhanced chemical vapor deposition (PE-CVD) of polymer films has many advantages that overcome these problems. Recently, a use of low-k fluorinated amorphous carbon (a-C:F) fi lms, that have both crosslinked and PTFE (polytetrafluoroethylene)-like structures, has proposed.@footnote 1@ Now, a cla ss of materials is widely investigated using PE-CVD. Around 400°C thermal stability and the dielectric constant o f 2.3-2.7 are realized by controlling the fluorine concentration in the films. For an easier integration, a-C:F film is covered with SiO@sub 2@ that protect the a-C:F film during processing. Si-rich SiO@sub 2@ glue layer is used to maintain adhesion strength between them. Also, excellent gap filling was realized by u sing a biasing PE-CVD technique. The fabrication of globally planarized 3-lebel Al interconnect using a-C:F ILD achieved 50% reduction in capacitance. Now, a combination of Cu and low-k materials is most promising for the further reduction in RC delay. Also, lower deposition temperature of Cu is appropriate for the low-k materials that are typically less the rmally stable than SiO@sub 2@ films. The a-C:F deposition technology can also be applied to Cu wiring system. A damascen e structure with Cu wiring and a-C:F ILD was successfully fabricated and no reaction between Cu and fluorine was observe d.
@FootnoteText@
@footnote 1@K. Endo, MRS Bulletin 22, 55 (1997).