The logic ICs are targeting an higher packing density for increased performances and cost effective manufacturing. In the ‘front-end’ part of the process (i.e. the transistor and the lateral isolation), this higher integration is obtained - along with higher operating frequencies and reduced power consumption - in shrinking the feature sizes. As the materials stay basically the same (i.e. Si and SiO@sub 2@), this trend stresses strongly the photolithographic techniques : the etch process has to define structures at the atomic level ; selectivity, CD and profile are key parameters to control in these features with such an high aspect ratio. The density of the interconnections (‘back-end’ part of the process) can be improved by shrinking the feature sizes and by increasing the number of metal layers. Unfortunately, if one stays with the classical Al/SiO@sub 2@ system, while shrinking the metal pitch, the performance of the integrated circuit is degraded : there is thus a growing need to move to new materials (e.g. dual Damascene copper lines and insulators with a lower dielectric constant). Advanced developments will be required in the etching of these materials and, due to the introduction of the Damascene approach, the equipment set will be radically changed in a manufacturing line. The metallisation process impacts strongly the behaviour of the transistor : plasma induced damage during processing degrades the active devices and specific care need to be taken in order to minimize this detrimental effect. Finally, as the number of metal levels is increased, manufacturability is a major issue in the cost of the final product: improving the defectivity level of the interconnects is a key point, as more than half the process steps are now involved in the fabrication of the interconnection system.