Key frontend integration challenges for sub 0.25 µm technologies will be discussed. For device isolation shallow trench isolation (STI) has emerged as the main road; the different approaches for STI fill and planarization will be evaluated. For the transistor integration shallow retrograde wells, sub 5 nm gate dielectrics, dual work function gates and shallow source/drain junctions are the key technologies. Logic and DRAM applications are posing different boundary conditions for integration, thus leading to different solutions for the device architecture. For high packing density memory arrays and cell based designs selfaligned contact- and local interconnect schemes has to be integrated in the frontend process flow. As a DRAM specific topic the integration challenges for trench- and stack capacitors will be addressed.