AVS 45th International Symposium
    Electronic Materials and Processing Division Wednesday Sessions
       Session EM-WeM

Invited Paper EM-WeM7
Process Optimization of CMP of Dielectrics for ULSI Multilevel Metallization

Wednesday, November 4, 1998, 10:20 am, Room 316

Session: Fundamentals of Si Cleaning and CMP
Presenter: H.W.A. Treichel, OnTrak Systems, Inc.
Authors: H.W.A. Treichel, OnTrak Systems, Inc.
R. Frausto, Lam Research Corporation
A. Meyer, Lam Research Corporation
R. Morishige, Lam Research Corporation
S. Srivatsan, Lam Research Corporation
B. Withers, Lam Research Corporation
Correspondent: Click to Email
The push of leading edge ULSI manufacturing technologies toward the formation of sub 0.1 µm feature sizes places extreme performance demands on the processes and equipment used. At submicron line widths, the depth-of-focus was limiting technology and CMP emerged as an essential enabling technology for feature sizes of 0.35 µm and below to meet the stringent DOF requirements for next generation devices. Thus, CMP emerged quickly and has become quite sophisticated.@footnote 1@ Current CMP systems are adaptations from existing glass and silicon polishing tools. These platforms are based on a rotating head and a circular platen. Lam Research recently introduced a new revolutionary linear track system (Aurora), an automated CMP machine which has a belt platen module that is capable of linear speeds up to 120 to 150 m/min, especially designed for planarization. This results in less pattern sensitive planarization, very high removal rates, and excellent uniformities at low head pressures. CMP is a very complex process. Its performance is determined not only by machine controlled parameters like belt speed, down force, and more, but also by consumables, pad conditioning and wear.@footnote 2,3@ In order to clarify the role of numerous factors as control parameters, extensive evaluations have been performed. This article reports on specific improvements in LPT technology. It also describes the major dependencies of machine parameters versus experimental results and finally highlights selected optimized CMP processes. @FootnoteText@ @footnote 1@R. DeJule, Semiconductor Int., 11, 15 (1996) @footnote 2@S. Sivaram, H. Bath, R. Leggett, A. Maury, K. Mennig, and R. Tolles Solid State Technology, 5, 87 (1992) @footnote 3@L.M. Cook, J.F. Wang, D.B. James, and A.R. Sethuraman Semiconductor Int., 11, 141 (1995)