Advanced CMOS device manufacturing requires levels of contamination which 20 years ago would have been considered science fiction. Particulates, metals, organics, haze, and residue from sacrificial films represent critical yield issues for DRAM and logic devices. Accurate and precise measurement of these species also represents an incredible challenge. The use of TRXRF, SIMS, EDX, and XPS as surface contaminant metrology techniques will be discussed. In many cases the contrast between metrology and analysis has not yet been fully explored. The use of non-destructive inline contaminant metrology is becoming much more important as the wafer size increases from 200 to 300mm. Quick turnaround time is needed for fast problem solving, while the ability to send a wafer for subsequent processing after measurement is valuable for superior problem solving. In addition, correlation of inline measurements with end of line yield is the only relevant method of discovering problems. Any inline defects which do not correlate with end of line yield are usually irrelevant. Specific areas of cleaning technology to be discussed are pre-cleans for thin gate oxides, pre-furnace cleans for metal gates and other metal gate technology, sidewall polymer removal for polysilicon gates, self-aligned cobalt and titanium silicides, sidewall polymer removal for aluminum lines, corrosion of copper and aluminum lines, contamination from new materials (such as ruthenium or BST), and copper processing.