Invited Paper PS-TuM5
Prediction and Control of Fluctuation of Etching Properties by Simulation Technology

Tuesday, October 31, 2017, 9:20 am, Room 23

Fluctuations of etching properties such as the etched profile and damage distribution can affect the performance of advanced CMOS devices, making the prediction and control of these properties vital for mass production. However, the fluctuations mechanisms are not perfectly understood because of equipment limitations in the plasma monitoring systems used in mass production. Therefore, as a predictive technology, a plasma etching simulation was developed that considers the physical and chemical aspects of the plasma and the etched surface.

We modeled CH_xF_y plasma for SiN etching with a CCP system, taking into account the interaction between the bulk region and the chamber wall surface, and simulated the hydrogen (H) density distribution and H Balmer line emission (virtual OES) [1][2]. From comparisons with experimental OES, the reaction probabilities of H with varying chamber wall conditions (Si, SiO₂, polymer) were derived as 0.5, 0.06, and 0.1, respectively. Using these values, the incident H radical flux was calculated, and found to correlate with the SiN etch rate. This signifies that flux fluctuation is important for controlling the SiN etch rate.

To predict the etched profile and damage distribution for SiN, SiO₂, and Si etching, we developed a new simulation technique using an extended 3D voxel model. This included a Slab model [3] that divides the surface region into several thin slabs and time-dependently solved the surface reactions of its reactive and deposition layers, as well as the depth. We demonstrated SiN sidewall (SW) etching for MOSFET and bulk FinFET with CH_xF_y plasma, successfully describing the etching properties. In addition, a local damage distribution can be seen around the SW edge and in the Si fin, which is difficult to find by experimental analysis. Furthermore, our simulation found that a large amount of Si damage in the Si substrate is caused during SiO₂/Si contact hole etching despite the high SiO₂/Si selectivity (>20) [4], which also exhibits time-dependence. Also, fluctuations of the CD and the Si recess during Si gate etching by HBr/O₂ plasma are greatly affected by the byproduct (SiBr_x), exhibiting a dependence on the factor (R_G+R_S)S that includes the wafer (R_G) and chip (R_S) open area ratios, and pattern solid angle (S) [5].

These simulation technologies give us useful knowledge for optimizing the chamber wall condition, plasma etching process, and pattern design for advanced CMOS devices.

[1] Kuboi et al., JJAP 49, (2010) 08JD01.

[2] Fukasawa et al., JJAP 48, (2009) 08HC01.

[3] Kuboi et al., JVST A 33, (2015) 061308.

[4] Nakamura et al., JVST A 25, (2007) 1062.

[5] Kuboi et al., JVST A 31, (2013) 061304.