| AVS 64th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Tuesday Sessions |
| Session PS-TuM |
| Session: | Advanced FEOL/Gate Etching |
| Presenter: | Yohei Ishii, Hitachi High Technologies America, Inc. |
| Authors: | Y. Ishii, Hitachi High Technologies America, Inc. M. Walker, Hitachi High Technologies America, Inc. R. Scott-McCabe, Hitachi High Technologies America, Inc. A. Yu, Hitachi High Technologies America, Inc. K. Okuma, Hitachi High-Technologies Corp., Japan K. Maeda, Hitachi High Technologies America, Inc. J. Sebastian, Hitachi High Technologies America, Inc. J. Manos, Hitachi High Technologies America, Inc. |
| Correspondent: | Click to Email |
As a result of miniaturization by the semiconductor industry to follow the pace of Moore’s law, new design approaches to manufacturing have been introduced. Logic device structures have transitioned from traditional planar designs to three dimensional Fin-type Field Effect Transistors (FinFET). This structure change has achieved improved device characteristics such as higher drive currents and lower transistor leakage. To further enhance FinFET electrical performance, a potential approach is the use of high mobility channel materials such as silicon germanium.
In current fabrication schemes, achieving vertical fin profiles and controlling RIE lag are typical issues associated with the fin etch process. However, with the use of silicon in n-FETs and silicon germanium in p-FETs, new etching challenges such as material-dependent etching rate differences have emerged. During the fin etching process, the silicon and silicon germanium must now be etched simultaneously. Silicon germanium etching characteristics have been studied and the results indicate that, with conventional halogen chemistries, the etch rate of silicon germanium is greater than silicon [1]. Should future technology nodes adopt silicon-germanium as a high mobility channel material, etching processes must consider how to control these material-dependent phenomena.
In this presentation, we will introduce an etching process which can be used for dual channel SiGe/Si fin etching. The result shows that the etched amount difference between silicon germanium and silicon can be controlled from a positive value (silicon germanium etching rate is greater than silicon etching rate) to a negative value. Surface analyses were also utilized to further understand the process and the mechanism. Details will be discussed in this presentation.
[1] G.S. Oehrlein, Y. Zhang, G. M. W. Kroesen, E. de Fresart, and T. D. Bestwick, Appl. Phys. Lett. 58, 2252 (1991)