AVS 64th International Symposium & Exhibition
    Plasma Science and Technology Division Friday Sessions
       Session PS+NS+SS+TF-FrM

Invited Paper PS+NS+SS+TF-FrM3
Solving the Grand Challenges of Plasma Etch with Concurrent Engineering

Friday, November 3, 2017, 9:00 am, Room 23

Session: Atomic Layer Etching II
Presenter: Mingmei Wang, TEL Technology Center, America, LLC
Authors: M. Wang, TEL Technology Center, America, LLC
P.L.G. Ventzek, Tokyo Electron Limited
A. Ranjan, Tokyo Electron Limited
Correspondent: Click to Email

A consequence of multiple patterning approaches enabling Moore’s Law scaling to continue through 10nm to 7nm and beyond is that plasma dry etch process faces unprecedented challenges. “Scaling” of plasma etch to seemingly impossible capabilities is the key to meeting Moore’s Law scaling. For example, etch process must achieve extremely high (almost infinite) selectivity in applications where self aligned patterning schemes are involved. Etch process is also required to achieve less than half nanometer (atomic scale) CD variations across 300mm wafers including the important “extreme edge” area as small as 2mm exclusion. These are but two examples of etch grand challenges. While the process requirements push the hardware design to the limits, understanding of process mechanisms becomes the most critical bottleneck to explore process regimes that are able to satisfy the most challenging patterning requirements. In fact, without process understanding at the atomic scale, it is difficult to imagine a means to innovate hardware designs.

In this talk, we will discuss concurrent engineering approaches including both modeling and experiment to understand and develop etching processes that meet grand challenge requirements. The core of the approach is an integrated chamber scale HPEM (Hybrid Plasma Equipment Model)-feature scale MCFPM (Monte Carlo Feature Profile Model) model [1]. The concurrent engineering approach comprises stages of development and prediction capability tests using both blanket wafer and patterned stack data and finally process parameter optimization. By using this approach, we are able to provide insights on how to resolve grand challenges in plasma etch with a minimum of engineering resources. The presentation will survey both experimental and computational results representing a few case studies in SAC quasi-ALE [2], Si ALE, organic etch CD uniformity, and LER/LWR improvement in EUV resist patterned sample etch. Furthermore, insights into the relationship between chamber function and critical surface interactions will be discussed.

[1] M.Wang and M.Kushner, J. Appl. Phys 107, 2010.

[2] M.Wang, P. Ventzek, A. Ranjan, J. Vac. Sci. Technol. A 35, 2017.