Invited Paper PS+AS-MoM8
Damage Free Plasma Etching Processes of III-V Semiconductors for Microelectronic and Photonic Applications

Monday, October 30, 2017, 10:40 am, Room 23

Due to their inherent advantages of direct bandgap and high electron mobility, III-V semiconductor materials are today widely used as active materials for a wide range of applications including high-speed and power electronic devices, and many types of opto-electronic and photonic devices. Recent progress in both molecular wafer bonding technology and monolithic heteroepitaxy let envisage the integration of III-V semiconductors directly on a Silicon platform. If successful, such integration paves the way for the emergence of highly performant devices, taking advantages of both III-V unique properties and the maturity of Si processing. Some promising examples are the use of high mobility III–V channel materials to extend the performance of Si CMOS, or the unification of electronics and photonics by combining photonic components with a silicon platform for next-generation optical interconnects. For all these future technologies, development of industrial processes for III-V semiconductors patterning is necessary. Plasma etching allows feature patterning with a nanometric control of the dimension, but one major drawback is the creation of defects in the vicinity of the etched surfaces, that can change the electro-optical properties of the semiconductor, and ultimately compromise the device performance. There is today a lack of knowledge on by which mechanisms and to what extent the plasma etching process induces damage at the III-V pattern sidewalls and the consequence it has on the device performance. The objective of this work is first to provide a better understanding of plasma-induced damage at the sidewalls of micro-nano-patterned III-V semiconductors by establishing a direct link between structural and chemical modifications induced by plasma etching, and opto-electrical properties. Based on such comprehensive know-how, the second objective is to provide technological solutions to minimize this damage in order to propose low damage plasma process compatible with the fabrication of commercial devices. The present study mainly focuses on the plasma etching process development of InGaAs used as a high mobility channel in a FinFET for microelectronic applications and of InGaAs/InP heterostructures used as a laser in hybrid photonic integrated circuits. Etching experiments are carried out in industrial ICP reactors. The structural damage induced at the pattern sidewalls (amorphization, stoichiometry, roughness..) are evaluated by electronic microscopies, AFM and nanoauger spectroscopy. The optical properties of the III-V semiconductors at the pattern sidewalls are analyzed by cathodoluminescence.