Paper PS-TuM5
Advanced Interconnect Process Techniques with EUV Photolithographic Masks and Sub-50nm Pitch Structures

Tuesday, October 20, 2015, 9:20 am, Room 210B

As the semiconductor industry moves into the sub-10nm technology nodes, feature pitches below 50nm become ubiquitous. To avoid the complications of SADP processing, EUV photolithography is being explored as a means to continue direct patterning. This brings forth etch processing challenges in three ways: First, EUV resists are thinner, softer and suffer from greater LER than 193nm optical resists. Second, the small dimensions and tight pitches are causing old problems, once thought of as solved, to reappear. Pattern collapse, aspect ratio dependent etching, ion deflection induced profile bowing, and feature induced CD variation are a few examples. Third, new integrations seeking the use of self-alignment, including self-aligned etch are becoming more prevalent. These self-aligned methods at such small dimensions require innovated etch techniques in order to be enabled.

In this paper, we will discuss the theory behind the various process solutions used to solve these etch challenges. Bias pulsing was used to address aspect ratio dependent etching concerns, and gas pulsing was used to improve material and corner selectivity in a self align etch process. Dielectric etch process solution on a dual-frequency capacitively coupled plasma (CCP) system were applied to the EUV lithographic masks. Superimposing a negative DC voltage to control the emission of ballistic electrons along with chemistry balance was used to minimize feature-dependent etch CD bias. These innovative process options allowed for the development of dielectric RIE processes that hit target specifications in the demanding pitch and CD sizes generated by the EUV lithography.

This work was performed by the Research and Development Alliance Teams at various IBM Research and Development Facilities.