| AVS 62nd International Symposium & Exhibition | |
| Plasma Science and Technology | Tuesday Sessions |
| Session PS-TuM |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | Toru Hisamatsu, Tokyo Electron Miyagi Limited, Japan |
| Authors: | T. Hisamatsu, Tokyo Electron Miyagi Limited, Japan T. Oishi, Tokyo Electron Miyagi Limited S. Ogawa, Tokyo Electron Miyagi Limited Y. Kihara, Tokyo Electron Miyagi Limited, Japan M. Honda, Tokyo Electron Miyagi Limited, Japan |
| Correspondent: | Click to Email |
Multiple exposures with double (quadruple) patterning has been adopted due to recent advancements in miniaturization with mask patterning techniques, and as the technology continues to develop, EUV exposure will be used in the near future. Extending the current techniques into the next generation is approaching the limit to satisfy required fabrication specifications, as it is required to have fabrication control of less-than- a-nm-order.
In the patterning process, multilayer patterning with high accuracy to form a fine patterning is becoming critical, especially in regards to line-roughness (LER/LWR) reduction, pattern-size dependency reduction of ARDE origin, and selectivity enhancement of thin EUV-resist. Furthermore, patterning with universal CD shrinkage independent of the pattern types (hole, oval, L/S) is also being required.
To this date, challenges of precise CD controllability have been solved by combining DC-superimposed plasma which reduces line-roughness by its accelerated electron-beam to cure resist surface, followed by the Si coating effect and optimization of etch condition to form a protection layer on the surface[1,2]. However, it is evident that those current techniques will soon face the limit as the resist thickness is reduced with the employment of EUV exposure; therefore the breakthrough with the new approach is essential.
As a result of various feasibility studies put into effect for a problem solution of fine pattern formation, “fusion of ALD technology and etching” was confirmed to be very beneficial for its capability of atomic-level formation of surface protection film during the etch process. This technology enabled line-roughness reduction with pattern-size dependent CD shrink control, since the ALD step is used according to the optimum timing during the etch process, which forms proportional deposition on any type of patterns. This paper discusses the optimization of ALD step timing, its layer thickness and composition of corresponding etch flow, and introduces a possible solution to various patterning process issues without trade-offs. This technique enables atomic-level control during the etch process and thus, is promising for further miniaturization of the patterning process.
Reference
[1] M. Honda et al., AVS 60th Int. Symp. & Exhibit. (2013)
[2] M. Honda et al., Proc. of SPIE 8328-09 (2012)