| AVS 62nd International Symposium & Exhibition | |
| Plasma Science and Technology | Friday Sessions |
| Session PS+SS+TF-FrM |
| Session: | Atomic Layer Etching (ALE) and Low-Damage Processes II |
| Presenter: | Eric Hudson, Lam Research Corporation |
| Authors: | B. Finch, Lam Research Corporation H. Singh, Lam Research Corporation E.A. Hudson, Lam Research Corporation |
| Correspondent: | Click to Email |
CMOS devices have continued to scale dimensionally following the implementation of FinFET transistors. Self-alignment of the source and drain contact to the gate has been presented as an integration solution starting at the 22nm technology node1. This self-aligned contact (SAC) integration creates additional challenges and constraints on the etch process for the 10 nm node and beyond. Due to smaller feature dimensions, lithography overlay, and full contact wrap-around of the transistor fins, unprecedented etch precision is now required.
A novel approach for SAC oxide etching has been developed which addresses the many tradeoffs of this application using a directional atomic layer etch process (ALE) as reported by Hudson et al2. Key trade-offs to enable contact etching capability of CDs as small as 10 nm include SAC spacer loss, lack of profile control, and contact not-opens. This cyclic SiO2 ALE process repeats discrete unit process steps of fluorocarbon deposition and ion bombardment to achieve high selectivity of SiO2 to Si3N4 while simultaneously addressing these tradeoffs. Oxide removal rates can be precisely controlled with minimal removal of Si3N4 films, enabling a highly selective etch process. Anisotropic, directional etch behavior superior to traditional SiO2 etch is enabled, creating vertical oxide profiles. This capability is highly desirable for SAC etch applications as it maintains the integrity of the gate electrode spacer during etch. Experimental results showing the ability of this oxide ALE process to eliminate tradeoffs is presented
[1] C. Auth, et al, “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” accepted in VLSI Symp. Tech. Dig., Jun. 2012.
[2] E. Hudson, et al, “Highly Selective Atomic Layer Etching of Silicon Dioxide Using Fluorocarbons,” accepted in AVS 61st International Symp. & Exhibition, Nov. 2014.