AVS 60th International Symposium and Exhibition
    Plasma Science and Technology Tuesday Sessions

Session PS2-TuM
Advanced FEOL/Gate Etching

Tuesday, October 29, 2013, 8:00 am, Room 104 C
Moderator: G.Y. Yeom, Sungkyunkwan University, Republic of Korea


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  in Adobe Acrobat format  

Click a paper to see the details. Presenters are shown in bold type.

8:00am PS2-TuM1
Evaluation of Highly Selective ZrO2 and HfO2 based Hard Mask Stacks for sub 30 nm Node Dry Etch Pattern Transfer
J. Paul, X. Thrun, S. Riedel, M. Rudolph, Fraunhofer Institute for Photonic Microsystems (IPMS-CNT), Germany, S. Wege, Plasway, Germany, C. Hohle, Fraunhofer Institute for Photonic Microsystems (IPMS-CNT), Germany
8:20am PS2-TuM2
Approach to LER/LWR Improvement with Combination of DCS Technology and Newly Developed Resist Material
M. Honda, K. Kobayashi, Tokyo Electron Miyagi Limited, Japan, M. Yamato, K. Oyama, H. Yaegashi, H. Mochiki, Tokyo Electron Limited, Japan
8:40am PS2-TuM3 Invited Paper
Metrology and Linewidth Roughness Issues during Complex High-k/Metal Gate Stack Patterning for sub-20nm Technological Nodes
E. Pargon, M. Fouchier, CNRS-LTM, France, O. Ros Bengoechea, STMicroelectronics, J. Jussot, UJF, France, E. Dupuy, M. Brihoum, CNRS-LTM, France
9:20am PS2-TuM5
Possible Si Damage Formation and Redeposition in Vertical Gate Etching Processes by HBr Plasmas
Y. Muraki, H. Li, T. Ito, K. Karahashi, Osaka University, Japan, M. Matsukuma, Tokyo Electron Ltd., Japan, S. Hamaguchi, Osaka University, Japan
9:40am PS2-TuM6
Impact of Etch Processes Over Dimensional Control and LWR for 14nm FDSOI Transistor Gate Patterning
O. Ros, ST Microelectronics, France
10:40am PS2-TuM9
FinFET Patterning: Promises and Challenges of SIT^2 for Fin Formation for sub-40 nm Pitch Features
S. Mignot, GLOBALFOUNDRIES U.S. Inc., I.C. Estrada-Raygoza, H. He, IBM, K. Akarvardar, J. Cantone, GLOBALFOUNDRIES U.S. Inc., B. Doris, IBM, A. Jacob, GLOBALFOUNDRIES U.S. Inc., S. Schmitz, J. Lee, P. Friddle, M. Goss, Lam Research Corp
11:20am PS2-TuM11
Stack Patterning Challenges for the FinFET Architecture
A. Banik, S. Kanakasabapathy, S. Burns, A. Aiyar, M.J. Brodsky, IBM Corporation
11:40am PS2-TuM12
Mechanisms of Etching and Selectivity for FINFET Gate Low-k Spacer using RLSA™ Microwave Plasma Reactor with Radial Line Slot Antenna
A. Raley, B. Parkinson, A. Ranjan, S. Keisuke, K. Kumar, P. Biolsi, TEL Technology Center, America, LLC