Paper PS2-TuM11
Stack Patterning Challenges for the FinFET Architecture

Tuesday, October 29, 2013, 11:20 am, Room 104 C

The FinFET device architecture, presents certain new gate patterning challenges. The gate stack aspect ratio is higher, compared to previous planar generations. We will illustrate how this aspect ratio is due to the presence of fins and the need for higher overetch in the offset spacer patterning. Controlling the gate profile to be vertical in both isolated and dense lines is challenging as the gate height increases. Further, Double expose Double etch (DE²) has been the process of record since the 45nm node. This is driven by the need for better tip-to-tip control while maintaining across chip line width control (ACLV). It has typically relied on pattern assembly through DE², in the gate hardmask layers, followed by a transfer etch into the underlying gate polysilicon. In such a scheme, the dense-iso gate critical dimension (CD) variation is exacerbated by the tall gates needed for the FinFET architecture. Legacy techniques, such as higher ion energy in the polysilicon etch, are limited by the large overetch needed past the fin tops, and selectivity needed in that step.

We present in this paper, patterning sequencing options that reduce the dense-iso challenges for the unique FinFET geometry. We will present data that shows how Lithography and etch process modifications are needed to enable such modified patterning sequences.

This work has been performed by the independent SOI technology development projects at the IBM Microelectronics Division Semiconductor Research & Development Center, Hopewell Junction, NY 12533