Paper PS2-TuM6
Impact of Etch Processes Over Dimensional Control and LWR for 14nm FDSOI Transistor Gate Patterning

Tuesday, October 29, 2013, 9:40 am, Room 104 C

Microelectronic evolution still relies on higher transistor gate integration and transistor size reduction. The major issue related to transistor downscaling is the control at the nanometer range of two main variability sources: Critical Dimension uniformity (CDU) and the Line Width Roughness (LWR). Nowadays, the best lithography conditions allow the definition of photo-resist patterns with a minimum roughness of 4-5nm and a CDU at 3σ < 2.5nm (for 28nm technologies), which will be then transferred into the underlying layers by etch processes. To improve lithography performances, post-lithography treatments such as plasma treatments have so far been introduced to increase photo-resist stability and to improve LWR and CDU during pattern transfer. If such a strategy allows to meet the CDU and LWR requirements of the 32 nm technological node, we will show that the unique use of conventional post-lithography treatments is not anymore efficient to address the specifications of the latest CMOS and beyond CMOS technologies. They indeed introduce several pattern deformations such as resist flowing and gate shifting, that inevitably cause process variability. Thus, new patterning strategies have to be implemented to ensure CMOS downscaling.

In this study, we compare different etch chemistry combinations in order to define the best etch process condition to pattern a 14 nm Fully Depleted Silicon On Insulator (FDSOI) gate stack guaranteeing control over the main variability sources, CD uniformity and LWR. We show that a combination of photo-resist pre-treatments and an optimization of each material’s etch process are required to ensure process control during typical FDSOI gate stack patterning (consisting in Photoresist/Silicium Anti Reflective Coating (SiARC)/Carbon layer (SoC)/Oxide Hard Mask (HM)/Polysilicium/High-K Metal Gate (HKMG)). As an example, promising results over SiARC opening step show that the introduction of a new etch chemistry followed by an optimized trim step leads to better defined patterns and a 25% improvement over LWR compared to the values obtained after standard SiARC opening.