Critical Dimension (CD) Scaling and Pitch Scaling for the past several decades have sustained the Microelectronics Industry’s march along the Moore ’s law. Wavelength, Numerical Aperture & Immersion assisted index scaling have made possible such pitch scaling in a fashion relatively transparent to Etch. However with the technical and manufacturing challenges faced by Extreme Ultraviolet (EUV) wavelength scaling, Etch/Integration assisted Pitch Scaling is being explored. Ground rule challenges have grown exponentially since Sidewall Image Transfer (SIT) was proposed as such a technique for pitch halving.

 

We present herein SIT challenges for obtaining sub 80 nm pitches for Line space levels compatible with Front End of Line applications. Line Edge Roughness (LER) and Line width Roughness (LWR) measurements for these integration schemes will be presented with options to mitigate them.