AVS 56th International Symposium & Exhibition
    Manufacturing Science and Technology Thursday Sessions
       Session MS-ThA

Invited Paper MS-ThA1
Nanoelectrical and Nanomechanical Interconnect and Device Metrology for CMOS Extension

Thursday, November 12, 2009, 2:00 pm, Room C3

Session: Manufacturing Issues in Nanoelectronics, PV and SSL
Presenter: R.E. Geer, University at Albany
Authors: R.E. Geer, University at Albany
C.H. Chong, University at Albany
Y. Wang, University at Albany
Correspondent: Click to Email
So-called ‘equivalent scaling’ which is dominating the extension of CMOS from the ‘pure’ scaling regime places inordinate demands on interconnect performance both for conventional CMOS switch configurations as well as alternate switch materials (III-V, carbon-based). As a result, substantial advances are required in fundamental metrology measurements of thin film electrical continuity in conventional intra-core and core-core interconnects as well as innovative approaches for electrical and mechanical interconnect metrology for alternate CMOS material sets. Here, we present nanoscale electrical continuity profiling of ultra-thin barrier and Cu films for conventional interconnects as well as nanoscale electrical metrology of alternate material (graphene-based) interconnects. For the former, it is shown that sub 2-nm films, although electrical conductive, show local reduction in electrical continuity that correlate to line-edge-roughness in patterned interconnect test structures. In contrast, alternate interconnect materials (e.g. single-layer graphene) are shown to exhibit electrical uniformity although local defectivity and electrostatic doping (for the case of interconnect applications) must be sufficiently controlled for use in conventional CMOS geometries.