| AVS 55th International Symposium & Exhibition | |
| Plasma Science and Technology | Friday Sessions |
| Session PS2-FrM |
| Session: | Plasma Processing for 3-D Integration, Photonics, Optoelectronics, and Memory Devices |
| Presenter: | P. Dixit, Nanyang Technological University, Singapore |
| Authors: | P. Dixit, Nanyang Technological University, Singapore R. Chatterjee, Georgia Institute of Technology J. Miao, Nanyang Technological University, Singapore R. Tummala, Georgia Institute of Technology |
| Correspondent: | Click to Email |
In this paper, we present a novel multi-step etching technique to encounter the aspect ratio dependent etching (ARDE) characteristic of plasma etching process and to fabricate very high aspect ratio vertical through silicon vias. ARDE effect, which represents the reduction in etch rate at higher etching depth, is caused by the the depletion of etching radicals. The collisions of etching species with the outgoing reactions products and with the sidewalls, are also responsible for reduction in the etch rate. To maintain the constant etch rate and vertical sidewall profile, the depletion in the etching radicals should be compensated, which can be achieved by adding more etching radicals and plasma energy. To achieve this objective, we have proposed a multi-step etching technique, in which important DRIE parameters were gradually increased to maintain the constant etching flux . DRIE parameters, such as platen/coil power, SF6 and C4F8 flow rate, etching and passivation cycle duration, etc were increased in steps to provide 'additional etching species' needed at the bottom of the high aspect ratio etched features. At first, effect of individual parameters was investigated by varying a single parameter while keeping remaining parameters constant. 6 DRIE experiments were carried out to evaluate the effect of platen power on the etched profile (8, 10, 12, 14, 16 and 18 W). Similarly other experiments were performed to find the best parameter to overcome the depletion of etching radicals and to maintain the vertical etch profile. When the effect of individual parameters on etched profile was known, those parameters were chosen that gives the straight profile at relatively higher etch rate and with minimum undercut. Effect of platen power on controlling the perpendicularity of through-vias was found to be the most dominant among all parameters. A 200 nm aluminum layer was used as an anti-notching layer to prevent the lateral etching of vias at the bonding interface. Scanning electron microscope confirmed that the etching profile was completely vertical even at an etching depth as large as 510 micron. Using this technique, very high aspect ratio (>30), vertical through silicon vias having an opening dimension as small as 10 micron were fabricated. These DRIE etched through silicon vias were later electroplated to form copper interconnects, which are the most important building blocks for the next generation 3D stacking technology.