Invited Paper PS2-FrM5
Advancement and Characterization of 3D TSV Etch Applications

Friday, October 24, 2008, 9:40 am, Room 306

Implementation of TSV modules in production for 3DIC applications has become a technical and fundamental reality to contend with. Almost every semiconductor manufacturer is either directly working on TSV module design and development, or – if fabless, is working with partners for implementation of TSV modules. It is clear that CMOS Image Sensors (CIS) are leading the pack in implementation, with memory suppliers following closely. However, it is unclear at this time which memory segment will choose to implement TSV’s first; DRAM or Flash, perhaps for reasons more related to economics than technology. This talk will primarily focus on the etch requirements for the TSV module. Etch challenges can vary widely with different applications, such as CIS, Memory, or Logic. In addition, TSV etch challenges vary for different integration schemes, such as via first, via middle, or via last. Therefore, it is without surprise that the TSV etch development tasks have been quite challenging, and existing etch equipment were not immediately applicable for TSV implementation. Recent development and upgrades have been made to address these market requirements, whether for silicon or glass substrates. We will show results of a flexible process system that can etch the multi-film stacks in addition to the deep silicon required to form TSVs. Substrates are patterned with either photoresist or dielectric hard mask, ranging from the micron-level minimum geometries to several tens of microns. TSV etch examples will be demonstrated addressing different integration requirements ranging from patterned photoresist directly on silicon, to patterned photoresist on multi-stack films replicating some of the layers that may exist on processed IC wafers.