Paper PS1-WeM4
Clarification of Surface and Interface Structures Exposed to Inductively Coupled Plasma with Various Superposed Bias Frequencies and Its Implication in Plasma Damage Control

Wednesday, October 22, 2008, 9:00 am, Room 304

Plasma-induced Si substrate damage has become one of the critical issues in advanced MOSFETs with shallower junction in source/drain extension regions, since the damaged layer thickness will be in conflict with the device design margin (e.g. ~ 5 nm in 32-nm-node). The thickness is considered to be governed by plasma parameters such as ion energy distribution function (IEDF). With regard to plasma design, a plasma source driven by superimposed dual bias frequency was reported to control IEDF. For understanding the mechanism and suppressing the damage, the plasma-induced defects should be quantitatively estimated, and then, plasma should be optimized. We have preliminary quantified the damage induced by an inductively coupled plasma (ICP) reactor with superposed bias configuration by a photoreflectance spectroscopy (PRS)–based method.¹ Silicon wafers were exposed to an ICP reactor which apply bias powers with various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. The defect site density was determined by the PRS-based method. The surface and interface layers were assigned by spectroscopic ellipsometry (SE) and TEM. The surface layer growth and interfacial layer (IL) structure were studied by molecular dynamics (MD) simulation developed for the present process condition. The above structures were analyzed by stretching of capacitance-voltage (C-V) curves for the damaged samples. Based on the above comprehensive analyses, we found that an accurate model for plasma-damaged silicon surface structures should include an interface layer between the surface layer and the substrate, i.e., a conventional methodology can lead to an erroneous conclusion in addressing the structures. This bi-layer structure (surface stoichiometric SiO₂ and IL) was clarified by TEM, MD simulation and C-V test. The IL thickness increases with self-dc bias voltages. We also observed surface sputtering process (the decrease in surface layer thickness) and more severe damage at higher dc-bias voltages ( > 150 V), resulting in larger defect density (~ 10¹³cm^-2) in IL. Furthermore, it was quantitatively confirmed from PRS, SE and C-V techniques that interfacial layer growth and defect generation process depend on the superposed bias configurations with the same power. Quantitative measures and consideration of IL are key to future plasma and device designs.

@super
@super 1@Y. Nakakubo et al., Proc. Symp. Dry Process (2007) 287.