Paper PS1-WeA3
Impact on Wafer to Wafer Repetability of Cleanning/Coating Strategies in a 300mm ICP Plasma Reactor

Wednesday, October 22, 2008, 2:20 pm, Room 304

Nowadays in microelectronics, work focuses on the optimization of the 32 nm technological nodes and below. One of the key challenges to achieve the desired performance is to optimize well controlled and repeatable plasma etching processes leading to critical dimension control in the nm range. In gate etching processes one of the key parameter directly driving the process repeatability is the chamber reactor conditioning. Indeed, previous studies have shown that changes in the chamber wall conditioning are identified as one of the main origin of process drift leading to variations of key process parameters (etch rate, etch profiles, selectivity, and uniformity) inducing wafer to wafer variability. In this presentation we propose to investigate different chamber wall coating strategies such as SiOCl or Carbon rich coated films in 300 mm industrial ICP reactors. Correlation between morphological results and passivation layer formation on the silicon gate etch sidewalls using both type of coatings are performed using 300 mm in-situ XPS dedicated to chemical topography analyses. In addition, we will investigate the impact of the plasma chemistry on the process repeatability by investigating more specifically the influences of the SiCl4/O2 ratio used for chamber wall coating and of the SF6/CHF3 ratio used during poly gate patterning.