Paper PS1-WeA10
Impact of UV Plasma Light on Photoresist Pattern Linewidth Roughness during Gate Etch Processes

Wednesday, October 22, 2008, 4:40 pm, Room 304

Typical Polysilicon/gate oxide transistors in integrated circuits are made using a sequence of lithography and plasma etching steps. The decrease in critical dimensions (CDs) of integrated circuits imposes incredibly stringent requirements on lithography and etching processes. According to the International Technology Roadmap for Semiconductors (ITRS 2007), the gate CD for high performance logic devices will be 13 nm for the 32 nm technological node and requirements for linewidth roughness (LWR) will be of 1 nm (3σ). Best lithographic processes result in resist LWR of 4.5 nm (3σ) (measured by CD-SEM). Furthermore, it is now demonstrated that the roughness of the resist pattern sidewalls is partially transferred into the active layers of the gate stack during gate etch processes, impacting significantly the final device performance. In this study, CD-AFM is used to investigate the LWR generated during the lithography and plasma etching steps involved in the patterning of the gate transistors. CD-AFM is a technique that can measure LWR values by scanning resist patterns in 3 dimensions while CD-SEM techniques only bring information in 2 dimensions. Using appropriate experimental protocols, LWR can be estimated at +/- 7% by CD-AFM technique. Our results demonstrate that the efforts to minimize the final gate LWR can be largely concentrated on the etching steps preceding those used to pattern the active materials of the gate stack (Polysilicon, metals, High K) and more particularly those involving the photoresist patterns. Our results demonstrate that LWR of photoresist patterns can be strongly minimized during plasma exposure. For instance, after HBr or Ar plasma cure, the resist sidewalls can be smoothed leading to a decrease in LWR roughness of about 10%, while HBr/O₂ resist trimming processes will induce a 50% decrease in LWR (initial LWR ranging from 18 to11 nm) strongly minimizing the final LWR of the gate. Experiments using MgF2, Sapphire and glass windows to separate the influence of plasma radiation from the impact of ions and radicals reveal that UV light emitted by the plasma plays a crucial role in the resist pattern smoothening. Since the other materials involved in the gate stack are less sensitive to UV plasma light, our results demonstrate that the decrease in LWR can be mainly monitored by working on the plasma etch steps involving the photoresist, i.e resist trimming, BARC and hard mask opening steps.