AVS 55th International Symposium & Exhibition | |
Plasma Science and Technology | Tuesday Sessions |
Session PS-TuM |
Session: | Advanced Gate Etching |
Presenter: | O. Luere, Freescale Semiconductors, France |
Authors: | O. Luere, Freescale Semiconductors, France L. Vallier, LTM-CNRS, France E. Pargon, LTM-CNRS, France O. Joubert, LTM-CNRS, France |
Correspondent: | Click to Email |
Patterning sub-40 nm gates presents several challenges among which maintaining a tight CD control is one of the most challenging. To succeed, understanding the etching mechanisms in gate patterning processes is one of the challenge. In this work we have investigated the different physical phenomena involved during the patterning of silicon structures in SF6/CH2F2 based plasmas. The experimental work has been carried using a 200 mm etch platform connected, under vacuum, to an x-ray photoelectron spectroscopy surface analysis system. We have studied the impact of the SF6/CH2F2 ratio on the silicon etch rate, thickness and composition of the reactive layer formed on the bottom silicon surfaces of the etched structures, thickness and composition of the sidewall passivation layer formed on the silicon sidewalls and silicon profiles. Our results demonstrate that there are very good correlations between the silicon etch rates and reactive layers formed on the bottom silicon surfaces. Contrary to previous studies performed using HBr/Cl2/O2 chemistries our results indicate that there is no simple correlation between the thickness of the CFx passivation layer formed on the sidewalls and the final slope obtained in silicon. Our results demonstrate on the contrary, that even if very thin CFx based passivation layers are formed on the silicon sidewalls, significant slopes can be generated in silicon. Other experimental results will be shown to elucidate the etch mechanism driving the silicon gate etch profiles during SF6/CH2F2 plasma etching.