Invited Paper PS-TuM5
Etch Challenges at the 22nm Node and Beyond
Tuesday, October 21, 2008, 9:20 am, Room 304
As semiconductor manufacturing marches along according to its roadmap, the challenges of plasma etch at and around the transistor continue to increase. The last few generations have shown continued success to scale transistor gate lengths and simultaneously introduce novel transistor architectures with existing plasma etch technologies. Increasing numbers of new materials and continued scaling of material thicknesses and CDs promise to keep the pressure on plasma etch to deliver innovative solutions. Selectivities to multiple novel, thinner materials will be required. Etch tool environments may experience dramatic changes from traditional silicon or oxide etches and require “re-learning” of proper cleaning and conditioning. Even analysis of the structures being created becomes increasingly difficult as we march forward. Continued vigilance to the understanding of plasma etch and early identification of novel innovations to pattern, analyze and sustain integrated solutions across research, development and manufacturing is paramount to the success of plasma etch at the 22nm node and beyond.