Paper PS-TuM3
Etching Profile Simulation of Metal/High-k Dielectric HfO₂ in Chlorine Based Chemistry

Tuesday, October 21, 2008, 8:40 am, Room 304

With continuous downscaling of complementary CMOS devices, the physical thickness of SiO₂ gate dielectric is requested to be reduced to sub-micrometer regime. When the thickness is less than 1 nm, gate dielectric cannot satisfy the requirement of the low standby power CMOS devices beyond 32 nm technology node in 2013, due to the increase of gate leakage current, poly-Si gate depletion, and dopant penetration into the channel region. In order to overcome these issues, extensive studies to replace conventional poly-Si/SiO₂ with metal/high-k gate stack have been carried out. Among several candidates, HfO₂ attracts considerable attention because of its thermal stability at the interface with Si. It is well known, chlorine based chemistry is more suitable for the plasma etching of high-k dielectric HfO₂ than fluorine chemistry due to the high volatility of the etched by-products. One of the most promising procedures to etch metal/HfO₂ gate stack is Cl₂/O₂ plasma where high selectivity can be obtained over underlying Si and SiO₂. In addition, the etching residues made of Hf chloride may not be volatile in a low temperature condition. This leads to a significant adsorption at the sidewall, resulting in a variation of surface roughness (LWR: line width roughness). Thus, the etching profile of high-k material has strong dependence on substrate temperature. In this paper, the etching profile of high-k HfO₂ film is numerically predicted in the chlorine based chemistry in a two-frequency capacitively coupled plasma. Dependence of LWR on the substrate temperature will be mainly discussed by considering the redeposition of etched by-products (HfCl_xO_y) inside the pattern. Emphasis will also be given on the selectivity of HfO₂ etching over Si and SiO₂.