Paper PS-TuM10
Reduction of Si Recess during Gate Etching with RLSA Microwave Plasma Source

Tuesday, October 21, 2008, 11:00 am, Room 304

As the design rule of ULSI devices continue to be scaled down, the critical dimension (CD) and reduction of silicon recess will need to be precisely controlled.¹ In this study, poly gate etching was evaluated to reduce silicon recess with RLSA (Radial Line Slot Antenna) microwave plasma source. RLSA generates plasma just below top dielectric plate, and as the plasma diffuses forward the wafer, its density and electron temperature become low immediately. The gate stack which was used for experiments consisted of SiN/Poly/Gate-Ox (2nm)/Si. First, it was etched with Vdc=-150V and Si recess was observed with TEM by changing over etching percent 50%, 100%, and 150%. The profile of gate stack was getting straight as increasing over etching percent and Si recess was less than 1.1nm. Second, by optimizing etching condition with lower Vdc=-135V, Si recess was 0.8nm and the profile kept straight. We suppose not only Vdc but also plasma potential Vp are effective factor to reduce silicon recess since the maximum ion energy can be estimated by adding plasma potential and Vdc. Comparing Vp under the same bias power between RLSA and RF plasma by ion energy analyzer on the chamber wall, it was found that RLSA plasma had lower Vp than RF one. RLSA can provide low Vdc and Vp condition keeping gate stack straight. This unique plasma characteristics will be able to use post 22 nm node Si etch like 3D gate that needs less etching damage on Si surface.

¹ S. A. Vitale and B. A. Smith, J. Vac. Sci. Technol. B 21, 2205 (2003).