Paper PS-TuA2
What are the Limiting Factors for Etching sub-10nm Si Holes?

Tuesday, October 21, 2008, 2:00 pm, Room 304

Patterning transferring nanometer-scale semiconductor features with precision has pushed us to think of the ‘true’ limits for plasma etching. One of the possible limits plasma etching facing is what the smallest holes (vertical side wall holes) plasma etching can do. In this paper, we report the recent results of studying plasma etching of nanometer-scale features with a focus on sub-10nm holes into silicon substrates as an examples to study the possible ‘limits’ for pattern transferring by plasma etching. Using diblock copolymer self assembled nanometer-scale patterns as starting templates, we using different methods to shrink the dimensions of the nanometer-scale holes down to sub-10nm regime. We studied plasma etching challenges for etching nanometer-scale holes into silicon with different masks in different plasma chemistries and process conditions. The results indicate that the plasma chemistry, plasma conditions and parameters, substrate temperatures, and the characteristics of aspect ratio dependence all play roles in the etching processes of forming nanometer-scale holes in silicon substrates. Among all the factors, when hole diameters shrinking down to sub-10nm regime, the sidewall passivation formed during the etching of holes with vertical sidewall becomes the determining factor for how small holes can be etched into silicon substrates. The result agrees with the previous studies.^1,2 The impacts of mask materials and selectivity to etch sub-10nm holes will be also discussed.

¹ Y. Zhang, Plasma Etching of Nanoscale Features, http://meetings.aps.org/link/BAPS.2007.DAMOP.C3.3, Calgary (2007).
² J. J. Végh and D. B. Graves, Investigating Fundamental Etch Limits: Molecular Dynamics Simulations of Sub-10 nm Feature Fabrication, AVS 54th International Symposium, http://www2.avs.org/symposium2007/Papers/Paper_PS2-WeM11.html.