Paper PS2-TuM9
Investigation of 45nm Silicon Gate Etching Process Variability Contributors

Tuesday, October 16, 2007, 10:40 am, Room 607

In a semiconductor world more and more aggressive in term of device performance and market cost, the control of critical dimension for 45 nm poly gate and beyond appears as a big challenge. Indeed as conventional photolithography is not able to define the novel design targets, other strategies as the double patterning on complex stack are developed. But the introduction of such complex process will induce additional sources of dimension variability and so alter the final functionality of the device. In this way, the research of the variability contributors from lot to lot, wafer to wafer, site to site will be the keys of an understood and controlled process. Some new parameters such as Line Edge Roughness (LER) will have to be considered. This presentation will focus on profile and dimension variability studies of the different steps of a gate stack process integrating a Hard Mask. Moreover we will investigate the impact of the 300 mm industrial ICP chamber walls conditioning strategies on the gate morphology. Chemical topography analyses by X-Ray Photoelectron Spectroscopy (XPS) will be performed to correlate the morphological results with passivation layer composition, deposited during the silicon etch process.