| AVS 54th International Symposium | |
| Plasma Science and Technology | Tuesday Sessions |
| Session PS2-TuM |
| Session: | Advanced Gate Etch |
| Presenter: | N.C.M. Fuller, IBM TJ Watson Research Center |
| Authors: | N.C.M. Fuller, IBM TJ Watson Research Center M.A. Guillorn, IBM TJ Watson Research Center Y. Zhang, IBM TJ Watson Research Center W.S. Graham, IBM TJ Watson Research Center E.M. Sikorski, IBM TJ Watson Research Center |
| Correspondent: | Click to Email |
Scaling of device dimensions for 32nm and beyond technology nodes demands process, integration and tooling innovations to meet feature profile, line edge roughness (LER) and line width roughness (LWR) requirements. To these ends multi masking schemes have been employed to attempt to enable scaled devices and reduce LER/LWR constraints. Further, we have utilized various process conditions to increase the mechanical integrity of patterning materials in such multi masking schemes patterned with mixed electron beam and optical lithography. This methodology has enabled 20nm gates on a 60nm pitch with 0.5-1.0nm improvement in post lithography LER/LWR and 100% physical yield. These and other results will be presented and discussed.