AVS 54th International Symposium | |
Plasma Science and Technology | Tuesday Sessions |
Session PS2-TuM |
Session: | Advanced Gate Etch |
Presenter: | C. Park, SEMATECH |
Authors: | C. Park, SEMATECH B.S. Ju, SEMATECH S.C. Song, SEMATECH M. Cruz, SEMATECH B.H. Lee, IBM R. Jammy, IBM |
Correspondent: | Click to Email |
One of the technical hurdles for implementing high-k / metal gate in advanced CMOS is high threshold voltage (Vth) in p-MOSFETs. Recently, it was shown that the Vth of p-MOSFETs can be lowered by using Ru compounds as a metal gate on HfSiO high-k dielectric. Gate etch requires good local and global etch uniformity across the wafer without damaging the underlying gate dielectric. Unlike Ru or RuO2 films, Ru compounds have high etch resistance with conventional etch chemistries, which imposes a significant technical challenge on gate stack patterning. It is possible to etch Ru compounds by applying higher than normal bias power. A high bias power etch, however, poses the high risk of forming either a micro-trench or footing on the pattern sidewall and causing a rough patterned sidewall as well as punch-through of the gate dielectric. It was demonstrated that ion implant could modify the bond structure of Ru compounds, so that they could be etched in a highly controlled manner with O2/Cl2 plasma. Optimum implant condition, which enables plasma etch of the Ru compounds, was found by splitting of implant energy and dose conditions. The effects of the ion implant on film thickness, bonding of Ru compounds, and knock-on of Ru compounds and gate dielectric into silicon substrate were also studied.