Paper PS2-TuM3
Nitride Spacers Dry Etching for sub-20nm HfO2 - Metal Gate on Fully Depleted SOI

Tuesday, October 16, 2007, 8:40 am, Room 607

Fully Depleted Silicon on Insulator is one of the most promising MOS transistors fabrication technologies to address low power and high speed applications challenges. Due to the very thin channel silicon thickness, selective epitaxial growth is mandatory to raise source and drain areas. So in addition to there classical uses as sidewall for ion implantation, spacers play a major role to avoid leakage current between metal gate and raised source and drain. On this way new constraints appear for nitride spacer dry etching. An accurate control of etch polymers is mandatory to allow a good performance of the next step, while a very high selectivity to thin silicon, silicon dioxide and HfO2 materials is required to avoid any silicon surface damage or HfO2 modification. Indeed, typical HfO2 thickness is less than 3 nm, thin silicon film is 10 nm or less while silicon dioxide hard mask on top of the gate must not be impacted. Moreover, two different approaches can be used for gate stack building. In the "spacer first approach", the nitride layer is deposited over the HfO2 material then spacers are etched, while in the "spacer last approach", the HfO2 is etched before nitride layer deposit. This affects the requirements for spacer etch, resulting in two different dry etch processes. These processes were developed in a DPS2 (Decoupled Plasma Source) Applied Material reactor either with a CH2F2 based chemistry or a CF4/HBr based chemistry. Etch rates, selectivities and non uniformities were optimized by adjusting gas ratio, source and bias RF power. SEM Cross sections, SEM-CD and TEM demonstrate good spacers profile and metal gate coverage. A 1.5 nm range spacer size control has also been reached, although spacer size adjustment by use of the overetch step seems to be limited. Plasma impact and selectivity to HfO2 and Silicon were measured by ellipsometry and XPS analysis. Results show no consumptions for HfO2 and less than 1.5 nm for silicon. A CFx polymer deposition allows high selectivities and no HfO2 modification. Post nitride dry etch XPS and particle measurement show also that HF wet chemistry is required to fully achieve High-K removal and optimize next integration steps. From these experiments, robust processes were developed. Electrical test of sub-20nm HfO2 and TiN Metal Gate on Fully Depleted SOI will be presented with the two integration schemes. This work has been carried out within the frame of Léti/Minatec-Crolles2 alliance program.