AVS 54th International Symposium | |
Plasma Science and Technology | Tuesday Sessions |
Session PS2-TuM |
Session: | Advanced Gate Etch |
Presenter: | T. Morel, STMicroelectronics France |
Authors: | T. Morel, STMicroelectronics France S. Barnola, CEA-LETI France O. Joubert, CNRS/LTM France |
Correspondent: | Click to Email |
Continuing downscaling of structures involved in advanced CMOS devices brings new complexity in plasma etching processes. The introduction of new materials, (metal gates, high-k dielectrics) to avoid the poly depletion effect and to minimize the equivalent oxide thickness, requires new dry etch approaches. Innovation proposed here is the use of thin MOCVD tungsten or tungsten nitride layers (10nm) to achieve PMOS devices on 300mm wafers. In this work, we characterized both metal layers by angle resolved X-ray Photoelectron Spectroscopy (XPS) and X-Ray Reflectometry (XRR). It is found that W and WN layer present differences in terms of oxygen and carbon concentration and density. To get a better understanding of interfaces between the different layers of a complete gate stack (Poly-Si / TiN / WN or W / high-k), Secondary Ion Mass Spectroscopy (SIMS) and XPS depth profiling were performed. The characterization of as-deposited and integrated tungsten alloy revealed variations between both metals that involved two different strategies to achieve good profile in patterned metal gate electrode. Concerning the process development, etch rates of W and WN were carried out in chlorine and fluorine based chemistries on a 300mm ICP tool with in-situ optical emission spectroscopy and in-situ interferometer. With the support of ion mass spectroscopy and quasi in-situ XPS, etch mechanisms of tungsten alloy were identified. Finally, the integration of W and WN etch into a multiple steps process for sub 45nm metal gates were investigated. Cl2-O2 and Cl2-O2 with additional fluorine are the proposed solutions to control, respectively, the profile of tungsten nitride and tungsten, without damaging the passivation on the Poly-Si sidewalls.