Invited Paper PS2-TuM11
Plasma Etching in the Era of Intensive Integration Innovation

Tuesday, October 16, 2007, 11:20 am, Room 607

Driven by relentless pursuit of Moor’s law, plasma etching advances at a rate never before seen in the history of this IC processing technology. New challenges are posed by several significant co-emerging trends: 1. Pattern fidelity requirements within wafer and lot reach sub nanometer, i.e. atomic resolution. 2. Plasma Etching is now an integral part of pattern generation (resist trim, double pattering, multilayer resist schemes). 3. Aspect ratios increase almost inverse proportional to the nominal line width for any given technology node reaching 100:1 for capacitor silicon etches and 40:1 for capacitor dielectric etches. 4. The number of potential new material candidates and their possible combinations in future stacks is exploding. At a first glance these challenges are well known and represent just another incremental tightening of known requirements. In this paper, we will show that these trends lead to three new paradigms in plasma etching: divergence of plasma etch applications, convergence the required process space to cover these applications and the need for precision chamber matching. We will discuss the consequences for plasma etch engineers and show examples for how Applied Materials Etch is responding to these new paradigms today to provide productive solutions for whatever device and integration engineers hold in store for the plasma etch community.