| AVS 54th International Symposium | |
| Plasma Science and Technology | Monday Sessions |
| Session PS2+MS-MoM |
| Session: | Plasma Etching for Advanced Interconnects I |
| Presenter: | Y.-D. Lim, Sunkyunkwan University, Korea |
| Authors: | Y.-D. Lim, Sunkyunkwan University, Korea S.-H Lee, Sunkyunkwan University, Korea C.-H. Ra, Sunkyunkwan University, Korea W.J. Yoo, Sunkyunkwan University, Korea |
| Correspondent: | Click to Email |
Three dimensional (3D) integration using chip-to-chip interconnects is currently receiving great attention since it can bring about substantial advantages in high packing density, low power consumption and high speed operation over planar circuits integration. Deep etching of high aspect ratio vias is known be the most critical step to realize the 3D interconnects. When the Bosch process which alternately introduces SF6 for isotropic etching and C4F8 for sidewall passivation is implemented to form deep via holes, the formation of scallops along the sidewall is unavoidable and poses a serious obstacle to scale down design rule in this scheme. In this work, we investigated methods to remove scallops using post O2 based plasma treatment assisted by subsequent HF based wet etching treatment, when inductively-coupled plasma etching had been applied to form various via hole sizes down to 2.5um with depths up to 100um. According to the experimental results, the removal of scallops was dependent on the via hole size, the orientation of scallop directed out of the sidewall, the combination of the post plasma etching chemistry and the subsequent wet etching chemistry, and the profile of etched structure. Furthermore, it was found that the removal of scallops is more effective for vias of larger and for more vertical structures. The technology developed in this work was proven to be suitable for subsequent electroplating of Cu interconnects.