Invited Paper PS2+MS-MoM1
Challenges for Microwave Plasma Etching of Low-k Dielectrics

Monday, October 15, 2007, 8:00 am, Room 607

Meeting post 32 nm etch process integration requirements with porous SiCOH and conventional plasma sources is a challenge as the SiCOH surface is decomposed by reactions induced by electron, ion, radical and UV radiation exposure. This exposure is inherent to most plasma systems making it difficult to achieve both high precision and damage free etching. Neutral beam etching has been developed to provide ion and UV radiation free and therefore damage free etching processes. Neutral beam etching by itself lacks the benefits of energy and chemistry control afforded by in-situ plasma processes. A Radial Line Slot Antenna (RLSA) driven surface-wave-plasma at 2.45GHz generates very high density plasma with high electron temperature in a region limited to just below the dielectric plate through which microwave pass. Both chemistry and energy control are achieved with the RLSA configuration. Plasma is transported to the wafer by diffusive transport through a low electron temperature region. An electronegative precursor gas (e.g., C4F8) is injected into the low electron temperature region so that dissociation is not excessive and a substantial negative ion population is generated near the wafer. An RF bias frequency 400kHz through the wafer provides ion acceleration without plasma generation. The combination of the low electron temperature electronegative downstream plasma with the low driving frequency facilitates charge damage free etching for all process conditions. Another consequence of the combination of plasma conditions near the electrode is that physical damage of SiCOH material is eliminated and k-value increase is minimized. This is achieved through dissociation control which results in the population reduction of small very reactive species such as H* and F* and the retention of sidewall polymer integrity. The unique plasma characteristics of the RLSA system will be described in this presentation with an emphasis on process performance for post 32 nm node CMOS fabrication.