Paper PS1-ThM3
3-D Profile Simulation of Silicon Etching: The Effects of Redeposition on Surface Roughening

Thursday, October 18, 2007, 8:40 am, Room 606

Line edge roughness (LER) on the sidewalls of gate electrodes in metal oxide semiconductor transistors is one of the most challenging issues in the microfabrication process today. Since the roughness does not scale with the feature size, the problem becomes more significant as critical dimensions get smaller for the future technology nodes. To understand LER, we have developed a 3-dimensional feature scale profile simulator to model and simulate the surface and sidewall roughening during the etching process of polysilicon in chlorine, hydrogen bromide and argon plasmas. We simulated the etching process using a dynamic Monte Carlo model, where the simulation domain is discretized into an array of cubic cells. The local surface conformation is fitted with a polynomial, which is used to compute the surface normal, scattering angle, and flux on the 3-D surface. Our results show that the roughening in physical sputtering process is a strong function of ion incidence angle and redeposition of sputtered materials. At normal ion incidence, the surface remains smooth, but at very grazing ion incidence, the surface is roughened along the ion beam direction. At grazing angle, the roughness is enhanced by the redeposition of sputtered materials. The simulator is also capable of modeling the transfer of roughness from the photoresist layer to the underlying layer during the gate etching processes.