Paper PS-TuP9
Dry Etching Technology of Cobalt Silicide for sub-60nm Gate Patterning using ICP Source with High Temperature ESC

Tuesday, October 16, 2007, 6:00 pm, Room 4C

Dry etching of CoSi₂ gate in sub-60nm design rule is successfully done using ICP (Inductively Coupled Plasma) source with high temperature ESC (Electro-Static Chuck). Vertical profile is achieved by forming a volatile Co byproduct reacted with Cl₂/Ar based plasma at 250°C of ESC temperature under relatively low DC bias voltage (~300V). Since Cl₂/Ar based plasma has low etch selectivity to polycrystalline Si (poly-Si) and gate oxide, O₂ and N₂ were added to reduce the recess of poly-Si layer which is remained beneath CoSi₂ layer during silicidation process. CoSi₂ layer used in this experiment was formed by sintering of sputtered Co layer on poly-Si layer. Dry etching of poly-Si is followed with both low temperature(~80°C) and high temperature (~250°C) ESC after CoSi₂ etching. For the poly-Si etching, HBr/O₂/He plasma was used to maintain high selectivity to gate oxide. However, even though poly-Si layer is recessed more than 200Å during CoSi₂ etching process, it was not possible to remove remaining poly-Si completely with HBr/O₂/He plasma. TEM and EDX are used to analyze surface of poly-Si, and thin metal layer containing Co is observed on the surface of polycrystalline Si layer. It is believed that this thin metal layer blocks etching of poly-Si. Therefore, removing the thin metal layer or preventing re-deposition of Co byproduct on polycrystalline Si layer during CoSi₂ etching will be necessary. Co as a barrier metal of bit line is also etched with vertical profile on high temperature (~300°C) ESC with Cl₂/Ar plasma. In this case, there was no remaining Co by-product since enough amount of Co OE is possible, resulting in complete removing of Co byproduct on ILD.