AVS 54th International Symposium | |
Plasma Science and Technology | Tuesday Sessions |
Session PS-TuP |
Session: | Plasma Science and Technology Poster Session |
Presenter: | H. Lee, Samsung Electronics, Korea |
Authors: | H. Lee, Samsung Electronics, Korea J.I. Shin, Applied Materials H.S. Lee, Applied Materials D.H. Kim, Samsung Electronics, Korea T.W. Kim, Applied Materials K. Shin, Samsung Electronics, Korea M.C. Kim, Samsung Electronics, Korea G.J. Min, Samsung Electronics, Korea C.J. Kang, Samsung Electronics, Korea J.T. Moon, Samsung Electronics, Korea |
Correspondent: | Click to Email |
Dry etching of CoSi2 gate in sub-60nm design rule is successfully done using ICP (Inductively Coupled Plasma) source with high temperature ESC (Electro-Static Chuck). Vertical profile is achieved by forming a volatile Co byproduct reacted with Cl2/Ar based plasma at 250°C of ESC temperature under relatively low DC bias voltage (~300V). Since Cl2/Ar based plasma has low etch selectivity to polycrystalline Si (poly-Si) and gate oxide, O2 and N2 were added to reduce the recess of poly-Si layer which is remained beneath CoSi2 layer during silicidation process. CoSi2 layer used in this experiment was formed by sintering of sputtered Co layer on poly-Si layer. Dry etching of poly-Si is followed with both low temperature(~80°C) and high temperature (~250°C) ESC after CoSi2 etching. For the poly-Si etching, HBr/O2/He plasma was used to maintain high selectivity to gate oxide. However, even though poly-Si layer is recessed more than 200Å during CoSi2 etching process, it was not possible to remove remaining poly-Si completely with HBr/O2/He plasma. TEM and EDX are used to analyze surface of poly-Si, and thin metal layer containing Co is observed on the surface of polycrystalline Si layer. It is believed that this thin metal layer blocks etching of poly-Si. Therefore, removing the thin metal layer or preventing re-deposition of Co byproduct on polycrystalline Si layer during CoSi2 etching will be necessary. Co as a barrier metal of bit line is also etched with vertical profile on high temperature (~300°C) ESC with Cl2/Ar plasma. In this case, there was no remaining Co by-product since enough amount of Co OE is possible, resulting in complete removing of Co byproduct on ILD.