| AVS 54th International Symposium | |
| Plasma Science and Technology | Tuesday Sessions |
| Session PS-TuP |
| Session: | Plasma Science and Technology Poster Session |
| Presenter: | I. Matthew, Advanced Micro Devices |
| Authors: | P.K. Subramanian, Advanced Micro Devices I. Matthew, Advanced Micro Devices T. Wallow, Advanced Micro Devices L. Tsou, IBM Corporation |
| Correspondent: | Click to Email |
As gate lengths shrink in 45nm technology node and beyond, the variation contributed by Line Edge Roughness(LER) becomes a larger proportion of the total CD variation Therefore, a reduction in the LER is one way of reducing the total variability of gate dimensions across a chip. In this paper we study evolution of the LER through the various process steps that end with the formation of a gate on the wafer. We examine the frequency components of the roughness as the wafer processed through various (lithography and etch) steps and examine the effects of each of these processes on the roughness spectrum. The advent of the immersion lithography and the attendant higher Numerical Aperture(NA) has led to the adoption of new schemes to reduce reflectivity. The impact of the new lithographic schemes on LER evolution is also examined. We also examine the effects of modifying etch process parameters and chemistry on the roughness spectrum. The effect of HBr plasma curing during etch processing on the LER is studied.