Paper PS-TuP3
Advanced Gate Stack Processes for sub-70nm CMOS Technology

Tuesday, October 16, 2007, 6:00 pm, Room 4C

The continued evolution of MOS (metal-oxide-semiconductor) transistor beyond the 90nm technology node will most likely be driven by advances in materials engineering and process integration. Fundamental changes in the materials used in the MOSFET (MOS field effect transistor) gate stack will become necessary as will novel processing techniques. High-k dielectrics can potentially extend scaling to thinner equivalent oxide thickness. However, in the production of very small size devices, the fine patterning technology is very important in order to manufacture the detailed device design based on the principle of the device operation. In this work, the dry etchings of new materials studied for the future CMOS devices are described. TiN as the metal gate electrode material and high-k gate insulators such as HfO₂ and Al₂O₃ are investigated. Etch rates and etch selectivity of TiN/high-k dielectrics gate-stack structures on Si substrate were investigated by varying the process parameters such as gas mixing ratio, source RF power, DC bias voltage, and process pressure. Plasma diagnostics were performed by quadrupole mass spectrometer (QMS) measurements and optical emission spectroscopy analysis. To investigate the etch residues of the high-K dielectric is generated by BCl₃/Cl₂/O₂ plasmas, the surface analysis on the dielectrics was performed using x-ray photoelectron spectroscopy (XPS).