AVS 54th International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS-MoA

Paper PS-MoA10
Plasma Source-Dependent Charging Damage Polarities in the Performance Degradation of MOSFETs with Hf-based High-k Gate Dielectrics

Monday, October 15, 2007, 5:00 pm, Room 607

Session: Plasma Processing for High k, III-V and Smart Materials
Presenter: M. Kamei, Kyoto University, Japan
Authors: M. Kamei, Kyoto University, Japan
K. Eriguchi, Kyoto University, Japan
H. Fukumoto, Kyoto University, Japan
K. Ono, Kyoto University, Japan
Correspondent: Click to Email

We report that the polarities of charging damage in n- and p-ch MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) depends on plasma sources, in contrast to those with conventional SiO2. In order to investigate the charging polarity in MOSFETs with the high-k gate stack (high-k) and those with SiO2 (SiO2), the gate leakage current, drain current - gate voltage, and capacitance - voltage measurements were conducted for at least 12 difference devices with different device sizes (antenna ratio) to evaluate the deviation. The electrical thicknesses by capacitance-voltage measurements are ~2.7 and ~7.4 nm for high-k and SiO2, respectively, while both devices have approximately the same physical thickness of 7 nm. ECR with the bias power of 200 W under two plasma conditions, Ar- and Cl-based gas mixtures, were utilized to induce the charging damage. The Langmuir probe and bias voltage measurements were carried out for correlating the electrical data to plasma parameters to understand the mechanisms. For Ar-plasma, high-k gate stacks were identified to suffer from negative charge trapping for both n- and p-MOSFETs, while SiO2, from positive charge trapping for pMOSFET. For Cl-plasma on the other, positive charge trapping was observed for n- and p-MOSFETs with high-k, in contrast to Ar-plasma. The observed unique features in high-k were attributed to the difference in the measured ion currents and electron densities between Ar and Cl plasmas as well as the effects of device polarities (n-/p-ch) and asymmetric energy band structures of high-k gate stacks on the stress configurations during plasma exposures. It is suggested that Ar- and Cl-plasmas exhibit different current sources (positive, negative, or bi-directional current sources) in response to device structures, in particular with high-k subject to charge trapping. In addition to the experimental result that high-k devices are more susceptible to plasma charging damage compared to SiO2 devices, it can be concluded that the observed plasma source-dependent charging polarity for high-k devices, in particular pMOS, should be considered in future device design rules and plasma process designs.