Paper MS-ThA6
Manufacturing Challenges and Method of Fabrication of On-Chip Capacitive Digital Isolators

Thursday, October 18, 2007, 3:40 pm, Room 615

Digital isolators permit high-speed data transmission in industrial and process control applications which involve hazardous voltage environments. Texas Instruments introduced on-chip capacitive isolation technology for digital isolated couplers which enables products to provide isolation voltage up to 7000Vrms and ~12000V surge capability. An innovative, robust method of manufacturing low noise, 10kV peak on-chip capacitive digital isolator integrated in a BiCMOS process flow is presented this paper. Silicon based on-chip capacitive isolators used here are fabricated in a high performance precision analog 5V, 0.3um digital CMOS process with extremely low noise performance, and uses a lightly doped bulk, p-type substrate. Electrical measurements of on-chip capacitors reported here follow UL 1577, IEC 60747-5-2, and CSA standards. These include two tests (a) ramped voltage test from 4kVrms to 10kVrms to force device breakdown, which would quantify highest allowable overvoltage (VIOTM) , and (b) pulsed constant voltage test where 50 short pulses of 8kV and higher (to force breakdown) at 1us intervals are applied to device under test (DUT) for both polarities of the device, bottom-injection and top-injection. In this work, on-chip capacitors used for high voltage isolation is built using a dielectric stack which is a combination of pre-metal oxide, and/or the various dielectrics from metal-1 to top-metal depending on whether the bottom electrode is moat or metal-1. The choice of dielectric employed in these capacitors is based on the results of a I-V measurement study which examined electrical breakdown voltage of various dielectric materials such as silicon nitride, silicon oxynitride, oxides such as HDP, TEOS at various film stresses. Silicon nitride and oxynitride have the best isolation properties and offer unique advantages in meeting the isolation capacitor requirements. The challenges of integrating silicon nitride and oxynitride films as part of a dielectric stack in CMOS metallization scheme, the influence of the order in which these films are deposited in the dielectric stack on isolation capacitor’s BVrms capability, pulse voltage performance, and device reliability are discussed. A model is developed to optimize dielectric film stresses in order to ensure isolation capacitor manufacturability by allowing wafer warpage to be maintained lower than the regime in which stepper chucking errors occur during downstream lithography processes.