Invited Paper MS-ThA3
MEMS Manufacturing in a High Volume CMOS Wafer Fabrication Facility

Thursday, October 18, 2007, 2:40 pm, Room 615

The original concept of the digital micromirror device (DMD) is a far cry from the current embodiment of today's devices. Design, process, and packaging innovations of the past decade have enabled Texas Instruments Digital Light Processing (DLP) devices capable of transitioning from on to off over 5000 times a second with native contrast ratios in excess of 4000:1. TI's philosophy is to manufacture the DLP MEMS device in an existing high volume CMOS wafer fab. This philosophy constrains the MEMS processes to be compatible with existing CMOS processes. Sharing the facility with standard CMOS allows TI to benefit from the economies of scale which exist in a high volume CMOS fab. The MEMS group has a dedicated team of development, integration, and process engineers embedded within the larger fab engineering organization. This facilitates synergy between the engineering teams and leverages the experiences of the larger organization. MEMS manufacturing has additional requirements not found on standard CMOS. Most MEMS are 3D devices requiring very tight control of film thicknesses to control the spacing between MEMS elements. Film stresses are of much greater concern in MEMS processing which has required additional control methodologies to be put in place to facilitate much tighter control than standard CMOS. TI DLP products utilize sacrificial photoresist layers to create the spacings between the MEMS elements. Standard lithographic tools and techniques are used to create the patterns and traditional plasma etching are used to define these features. The metal deposition process cannot use traditional sputter etch techniques due to the presence of photoresist on which the metal is being deposited onto. The metal must also be deposited at low temperatures to avoid resist reticulation. Photoresist stripping and cleaning techniques had to be developed which could integrate into the fab without affecting the sacrificial resist layers or inducing unwanted topography. Special care is paid to surface conditions to avoid stiction effects since metal-to-metal elements cone in direct contact during device operation. The final step prior to packaging is the plasma removal of the sacrificial resist layers to release the MEMS elements. Significant engineering effort has been dedicated to packaging since particles are a major source of defects. Control of the internal package environment is an area of special concern to control stiction during the lifetime of the product.