AVS 66th International Symposium & Exhibition
    MEMS and NEMS Group Tuesday Sessions
       Session MN-TuM

Paper MN-TuM4
Void-Free Copper Electrodeposition in Full Wafer Thickness Through-Silicon Vias with 10:1 Aspect Ratios

Tuesday, October 22, 2019, 9:00 am, Room A210

Session: MEMS, BioMEMS, and MEMS for Energy: Processes, Materials, and Devices II
Presenter: Rebecca Schmitt, Sandia National Laboratories
Authors: R. Schmitt, Sandia National Laboratories
L. Menk, Sandia National Laboratories
C. Sadler, Sandia National Laboratories
E. Baca, Sandia National Laboratories
A.E. Hollowell, Sandia National Laboratories
Correspondent: Click to Email

Copper-filled through-silicon vias (TSVs) are incorporated in microelectronic devices as a 3D integration technique to increase I/O per unit volume. Industry has incentivized thinning wafers to increase TSV density, but certain MEMS applications require full thickness substrates, thus creating a demand for mesoscale TSVs. Using a full thickness silicon wafer helps preserve wafer flatness during multi-layer device fabrication and conserves mass, often required in MEMS applications. Traditionally, a three-additive Cu deposition chemistry is used for TSV filling; however, in this work, a single-additive chemistry has been established to achieve bottom-up superfilling in high-aspect ratio features. This electroplating chemistry involves a mixture of CuSO4, CH4O3S or H2SO4, chloride, and a poloxamine suppressor additive. Cyclic voltammetry (CV) can be used to characterize the electrolyte and identify a hysteretic region, which is caused by suppressor breakdown at the cathode surface. This hysteresis corresponds to an operating window where void-free Cu filling of high-aspect ratio features can be achieved.

Previously, potentiostatic and galvanostatic deposition conditions for void-free filling were developed for nominally 100 μm diameter and 600 μm deep vias. Copper electrodeposition in TSVs with a 10:1 aspect ratio is currently under investigation. These TSVs have a 62.5 μm diameter etched into a 625 μm thick silicon-on-insulator (SOI) wafer. However, the conditions that resulted in void-free, bottom-up filling in 100 μm diameter TSVs have not translated to fill 62.5 μm geometries. In this work, electrolyte constituent concentrations, applied potential, and applied current were varied to analyze their effect on fill profile in 62.5 μm TSVs. Fill profiles were analyzed through cross sectioning and optical microscopy, as well as through X-ray CT scans. This work details the experimental approach associated with determining electrodeposition conditions for 62.5 μm diameter TSVs and presents the resulting fill profiles of copper in these vias.

Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525.