| AVS 66th International Symposium & Exhibition | |
| Electronic Materials and Photonics Division | Thursday Sessions |
| Session EM+AP+MS+NS+TF-ThM |
| Session: | Advanced Processes for Interconnects and Devices |
| Presenter: | M. Arslan Shehzad, Georgia Institute of Technology |
| Authors: | M.A. Shehzad, Georgia Institute of Technology A. T. Mohabir, Georgia Institute of Technology M.A. Filler, Georgia Institute of Technology |
| Correspondent: | Click to Email |
As conventional 2-D transistor scaling approaches its limits, 3-D architectures promise to increase the number of devices and reduce interconnect congestion. A process able to monolithically integrate single-crystalline group IV materials into the back-end-of-line (BEOL) may enable such designs. Here, we demonstrate the graphene-template assisted selective epitaxy (G-TASE) of single-crystal Ge on amorphous substrates at temperatures as low as 250 °C. This work represents a significant step forward for TASE methods, which have been largely limited to III-V and II-VI materials, bulk crystal templates, as well as higher temperatures. We specifically grow Ge nanostructures on graphene-on-oxide at the bottom of nanometer-scale oxide trenches by leveraging differences in group IV atom sticking probability between graphene and oxide surfaces. Raman mapping confirms the single crystallinity of as-grown Ge crystals. Time-dependent studies show a linear increase in Ge crystal height even after emerging from the oxide trench, indicating Ge atoms preferentially adsorb to the top facet under our growth conditions. Our studies also reveal that G-TASE is sensitive to the plasma process used to expose graphene in the oxide trenches. This work extends TASE to a new, technologically-relevant materials system and provides fundamental insight into the underlying physicochemistry.
KEY WORDS: silicon, germanium, epitaxy, graphene, selective deposition