AVS 66th International Symposium & Exhibition
    Electronic Materials and Photonics Division Thursday Sessions
       Session EM+AP+MS+NS+TF-ThM

Invited Paper EM+AP+MS+NS+TF-ThM3
The Role and Requirements of Selective Deposition in Advanced Patterning

Thursday, October 24, 2019, 8:40 am, Room A214

Session: Advanced Processes for Interconnects and Devices
Presenter: Charles Wallace, Intel Corporation
Correspondent: Click to Email
The edge placement error (EPE) margin on features patterned at tight pitches presents a difficult integrated challenge. Area selective deposition, chemically selective etches and the design of thin films for selectivity have risen to the top priorities in advanced patterning. The EPE control requirement creates a complex interaction between many integrated modules such as thin film deposition, etch (wet and dry), chemical-mechanical polish and lithography. The introduction of EUV lithography into the semiconductor patterning process has enabled some simplification of process architecture; however, has not decreased EPE margin enough to keep up with the pitch scaling requirements. Chemical selectivity is the most effective way to avoid EPE-caused failures on devices which lead to poor yield. Some of the limits to achieving selective growth solutions include development of self-assembled monolayers (SAMs), selective ALD/CVD growth and the metrology required to prove success. The development of manufacturable deposition chambers by the industry is a key requirement in order to adequately test the capability of these new process options.